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PART NUMBER:
± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
KXTF9-4100
Rev. 6
Jun-2011
Data Transfer Sequences
The following information clearly illustrates the variety of data transfers that can occur on the I 2 C bus and how
the Master and Slave interact during these transfers. Table 7 defines the I 2 C terms used during the data
transfers.
Term
S
Sr
SAD
W
R
ACK
NACK
RA
Data
P
Definition
Start Condition
Repeated Start Condition
Slave Address
Write Bit
Read Bit
Acknowledge
Not Acknowledge
Register Address
Transmitted/Received Data
Stop Condition
Table 7. I 2 C Terms
Sequence 1. The Master is writing one byte to the Slave.
Master
Slave
S
SAD + W
ACK
RA
ACK
DATA
ACK
P
Sequence 2. The Master is writing multiple bytes to the Slave.
Master
Slave
S
SAD + W
ACK
RA
ACK
DATA
ACK
DATA
ACK
P
Sequence 3. The Master is receiving one byte of data from the Slave.
Master
S
SAD + W
RA
Sr
SAD + R
NACK
P
Slave
ACK
ACK
ACK
DATA
Sequence 4. The Master is receiving multiple bytes of data from the Slave.
Master
S
SAD + W
RA
Sr
SAD + R
ACK
NACK
P
Slave
ACK
ACK
ACK
DATA
DATA
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